Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs encountered in the current IC market. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip™ developed by LSI Logic Corp. is an instance of a platform. The basic idea behind the platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the platform-based design may provide faster time-to-market and reduced design cost.
Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to be completed with the customer's unique IP. For example, RapidSlice™ developed by LSI Logic Corp. is an instance of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. The base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, the customer-designed function is merged with the pre-defined blocks and the metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function. In other embodiments, early-metal steps may be part of the pre-fabricated slice to reduce the time and cost of the customization step, resulting in a platform which is more coupled and specific. It is understood that a prefabrication step and a customization step may be performed in different foundries. For example, a slice may be manufactured in one foundry. Later, in a customization step, the slice may be pulled from inventory and metalized, which gives the slice its final product characteristics in a different foundry.
A slice such as RapidSlice™ may contain several RRAMs (Reconfigurable RAMs, or Redundant RAMs, or RapidSlice™ RAMs). Each RRAM is a set of memories of the same type that are placed compactly. RRAMs include built-in testing and self-repairing components and include a set of tools for mapping arbitrary customer memories (logical memories) to the memories from the matrix (physical memories). All RRAM memory ports are ports of customer memories. Ports of memories from the matrix are invisible from outside a RRAM. Thus, from the customer's point of view a RRAM is a set of customer memories.
A netlist describes the connectivity of an IC design. The problem of mapping a netlist to a design, which includes cells with predefined locations, often rises up during the development of chips based on the RapidChip™ technology, and/or FPGA. RapidChip™ technology uses RRAM cells that include pre-diffused internal memories and R-Cells. An R-Cell is a 5 transistor element configured by metal. In order to implement a customer memory mapped to RRAM, the memory may be represented as a tiling netlist of R-Cells and internal RRAM memories. Each memory of the tiling netlist may have already been assigned to the internal memory of RRAM. Therefore, what is needed is to map R-Cells of the netlist to the pre-diffused R-Cells of the RRAM.
Consider a set (called a template design or template) T of cells and pins with predefined locations in RRAM. T has no wires. Let N be a netlist such that it has cell types that are instantiated in T only. All the input and output pins of the netlist N are assigned to predefined pins of T. In order to obtain a design that implements the netlist N, pins of cells of T need be connected to pins of T that correspond to the pins of N by wires. Since the total wire length is an important consideration in IC design, thus, it is desirable to provide a solution with the sum of wire length being as minimal as possible.